[all-commits] [llvm/llvm-project] 54bb9e: [AMDGPU] Add -show-mc-encoding to setreg tests

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 54bb9e86498010c631a40dbd82617c433beea712
      https://github.com/llvm/llvm-project/commit/54bb9e86498010c631a40dbd82617c433beea712
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-09-16 (Wed, 16 Sep 2020)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll

  Log Message:
  -----------
  [AMDGPU] Add -show-mc-encoding to setreg tests

This is a pre-commit for D87446 "[AMDGPU] Enable scheduling around FP MODE-setting instructions"


  Commit: 90777e2924ec7f99a3f1b718a636f47036012514
      https://github.com/llvm/llvm-project/commit/90777e2924ec7f99a3f1b718a636f47036012514
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-09-16 (Wed, 16 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll

  Log Message:
  -----------
  [AMDGPU] Enable scheduling around FP MODE-setting instructions

Pre-gfx10 all MODE-setting instructions were S_SETREG_B32 which is
marked as having unmodeled side effects, which makes the machine
scheduler treat it as a barrier. Now that we have proper implicit $mode
operands we can use a no-side-effects S_SETREG_B32_mode pseudo instead
for setregs that only touch the FP MODE bits, to give the scheduler more
freedom.

Differential Revision: https://reviews.llvm.org/D87446


Compare: https://github.com/llvm/llvm-project/compare/aa4b0b755a02...90777e2924ec