[all-commits] [llvm/llvm-project] 56b333: [SelectionDAG] Move ISD:PARITY formation from DAGC...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 56b33391d3a42ef8e6fd1bcdcbcbb72bfb562092
      https://github.com/llvm/llvm-project/commit/56b33391d3a42ef8e6fd1bcdcbcbb72bfb562092
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-09-13 (Sun, 13 Sep 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/parity.ll

  Log Message:
  -----------
  [SelectionDAG] Move ISD:PARITY formation from DAGCombine to SimplifyDemandedBits.

Previously, we formed ISD::PARITY by looking for (and (ctpop X), 1)
but the AND might be separated from the ctpop. For example if the
parity result is multiplied by 2, we'll pull the AND through the
shift.

So to handle more cases, move to SimplifyDemandedBits where we
can handle more cases that result in only the LSB of the CTPOP
being used.