[all-commits] [llvm/llvm-project] 40f12e: [SLP] further limit bailout for load combine candi...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 40f12ef621d9fd2fb2dfe24f82b3f4f8c091f4ba
      https://github.com/llvm/llvm-project/commit/40f12ef621d9fd2fb2dfe24f82b3f4f8c091f4ba
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-09-11 (Fri, 11 Sep 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll

  Log Message:
  -----------
  [SLP] further limit bailout for load combine candidate (PR47450)

The test example based on PR47450 shows that we can
match non-byte-sized shifts, but those won't ever be
bswap opportunities. This isn't a full fix (we'd still
match if the shifts were by 8-bits for example), but
this should be enough until there's evidence that we
need to do more (this is a borderline case for
vectorization in the first place).