[all-commits] [llvm/llvm-project] c195ae: [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c195ae2f003261f2c25f569b07ae556dee57f17d
      https://github.com/llvm/llvm-project/commit/c195ae2f003261f2c25f569b07ae556dee57f17d
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-09-10 (Thu, 10 Sep 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
    M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll

  Log Message:
  -----------
  [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support.

Previously we could match fcmp+select to a reduction if the fcmp had
the nonans fast math flag. But if the select had the nonans fast
math flag, InstCombine would turn it into a fminnum/fmaxnum intrinsic
before SLP gets to it. Seems fairly likely that if one of the
fcmp+select pair have the fast math flag, they both would.

My plan is to start vectorizing the fmaxnum/fminnum version soon,
but I wanted to get this code out as it had some of the strangest
fast math flag behaviors.