[all-commits] [llvm/llvm-project] 480e7f: [AArch64][GlobalISel] Share address mode selection...

[Jessica Paquette via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 480e7f43a22578beaa2edc7a271e77793222a1c3
      https://github.com/llvm/llvm-project/commit/480e7f43a22578beaa2edc7a271e77793222a1c3
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2020-09-09 (Wed, 09 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Share address mode selection code for memops

We were missing support for the G_ADD_LOW + ADRP folding optimization in the
manual selection code for G_LOAD, G_STORE, and G_ZEXTLOAD.

As a result, we were missing cases like this:

```
@foo = external hidden global i32*
define void @baz(i32* %0) {
store i32* %0, i32** @foo
ret void
}
```

https://godbolt.org/z/16r7ad

This functionality already existed in the addressing mode functions for the
importer. So, this patch makes the manual selection code use
`selectAddrModeIndexed` rather than duplicating work.

This is a 0.2% geomean code size improvement for CTMark at -O3.

There is one code size increase (0.1% on lencod) which is likely because
`selectAddrModeIndexed` doesn't look through constants.

Differential Revision: https://reviews.llvm.org/D87397