[all-commits] [llvm/llvm-project] 6f1dbb: [X86] SSE4_A should only imply SSE3 not SSSE3 in t...
topperc via All-commits
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Tue Sep 8 11:59:13 PDT 2020
Branch: refs/heads/release/11.x
Home: https://github.com/llvm/llvm-project
Commit: 6f1dbbc17c03206040eeaaee71e5db961f2cac30
https://github.com/llvm/llvm-project/commit/6f1dbbc17c03206040eeaaee71e5db961f2cac30
Author: Craig Topper <craig.topper at intel.com>
Date: 2020-09-08 (Tue, 08 Sep 2020)
Changed paths:
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/Support/X86TargetParser.cpp
Log Message:
-----------
[X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend.
SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when
switching the code to being table based in D83273.
Fixes PR47464
(cherry picked from commit e6bb4c8e7b3e27f214c9665763a2dd09aa96a5ac)
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