[all-commits] [llvm/llvm-project] 8ee141: [AARCH64][RegisterCoalescer] clang miscompiles zer...

[simonwallis2 via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ee1419ab688ee2da2ac2cb0cf19db03f4c4742e
      https://github.com/llvm/llvm-project/commit/8ee1419ab688ee2da2ac2cb0cf19db03f4c4742e
  Author: Simon Wallis <simon.wallis2 at arm.com>
  Date:   2020-09-08 (Tue, 08 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    A llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir

  Log Message:
  -----------
  [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long

Implement AArch64 variant of shouldCoalesce() to detect a known failing case
and prevent the coalescing of a 32-bit copy into a 64-bit sign-extending load.

Do not coalesce in the following case:
COPY where source is bottom 32 bits of a 64-register,
and destination is a 32-bit subregister of a 64-bit register,
ie it causes the rest of the register to be implicitly set to zero.

A mir test has been added.

In the test case, the 32-bit copy implements a 32 to 64 bit zero extension
and relies on the upper 32 bits being zeroed.

Coalescing to the result of the 64-bit load meant overwriting
the upper 32 bits incorrectly when the loaded byte was negative.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D85956