[all-commits] [llvm/llvm-project] da79b1: [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: da79b1eecc65171f6ca0cda9b4f1970bd1503c17
      https://github.com/llvm/llvm-project/commit/da79b1eecc65171f6ca0cda9b4f1970bd1503c17
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-09-07 (Mon, 07 Sep 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-abs.ll
    M llvm/test/CodeGen/X86/abs.ll
    M llvm/test/CodeGen/X86/iabs.ll

  Log Message:
  -----------
  [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported.

Rather than using SELECT instructions, use SRA, UADDO/ADDCARRY and
XORs to expand ABS. This is the multi-part version of the sequence
we use in LegalizeDAG.

It's also the same as the Custom sequence uses for i64 on 32-bit
and i128 on 64-bit. So we can remove the X86 customization.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D87215