[all-commits] [llvm/llvm-project] 9b645e: [X86][AVX] Use lowerShuffleWithPERMV in shuffle co...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b645ebfff168fcf3cf29b21f49762a04d8ceb37
      https://github.com/llvm/llvm-project/commit/9b645ebfff168fcf3cf29b21f49762a04d8ceb37
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-09-07 (Mon, 07 Sep 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/insertelement-ones.ll
    M llvm/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
    M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
    M llvm/test/CodeGen/X86/vector-zext.ll

  Log Message:
  -----------
  [X86][AVX] Use lowerShuffleWithPERMV in shuffle combining to support non-VLX targets

lowerShuffleWithPERMV allows us to use the ZMM variants for 128/256-bit variable shuffles on non-VLX AVX512 targets.

This is another step towards shuffle combining through between vector widths - we still end up with an annoying regression (combine_vpermilvar_vperm2f128_zero_8f32) but we're going in the right direction....


  Commit: 5bb27e735d3ba561b93a12e07d79cd88a5bff338
      https://github.com/llvm/llvm-project/commit/5bb27e735d3ba561b93a12e07d79cd88a5bff338
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-09-07 (Mon, 07 Sep 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  Log Message:
  -----------
  X86AvoidStoreForwardingBlocks.cpp - use unsigned for Opcode values. NFCI.

Fixes clang-tidy cppcoreguidelines-narrowing-conversions warnings.


Compare: https://github.com/llvm/llvm-project/compare/3097427f93dd...5bb27e735d3b