[all-commits] [llvm/llvm-project] 8fb055: [VectorCombine] allow vector loads with mismatched...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 8fb055932c085da21f3b721995a06f42006744bd
      https://github.com/llvm/llvm-project/commit/8fb055932c085da21f3b721995a06f42006744bd
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-09-02 (Wed, 02 Sep 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
    M llvm/test/Transforms/VectorCombine/X86/load.ll

  Log Message:
  -----------
  [VectorCombine] allow vector loads with mismatched insert type

This is an enhancement to D81766 to allow loading the minimum target
vector type into an IR vector with a different number of elements.

In one of the motivating tests from PR16739, SLP creates <2 x float>
load ops mixed with <4 x float> insert ops, so we want to handle that
pattern in addition to potential oversized vectors created by the
vectorizers.

For now, we are assuming the insert/extract subvector with undef is
free because there is no exact corresponding TTI modeling for that.

Differential Revision: https://reviews.llvm.org/D86160