[all-commits] [llvm/llvm-project] ee6796: MIR: Infer not-SSA for subregister defs

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ee679638d75ca9a7f7d7be728fa069606dcc8ec7
      https://github.com/llvm/llvm-project/commit/ee679638d75ca9a7f7d7be728fa069606dcc8ec7
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-27 (Thu, 27 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
    A llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir

  Log Message:
  -----------
  MIR: Infer not-SSA for subregister defs

It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.


  Commit: 0034e00da0e5448b03e15eee0279736dab29c944
      https://github.com/llvm/llvm-project/commit/0034e00da0e5448b03e15eee0279736dab29c944
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-27 (Thu, 27 Aug 2020)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-and-trivial-mask.mir

  Log Message:
  -----------
  AArch64/GlobalISel: Fix missing function begin marker in test


  Commit: abc99ab5725636c17fa9c9ced0269f92bf5398cb
      https://github.com/llvm/llvm-project/commit/abc99ab5725636c17fa9c9ced0269f92bf5398cb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-27 (Thu, 27 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir

  Log Message:
  -----------
  GlobalISel: Implement known bits for min/max


Compare: https://github.com/llvm/llvm-project/compare/a40660551ea1...abc99ab57256