[all-commits] [llvm/llvm-project] 425873: [CodeGen][AArch64] Support arm_sve_vector_bits att...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 42587345a3afc52c03c6e6095db773358a1b03e9
      https://github.com/llvm/llvm-project/commit/42587345a3afc52c03c6e6095db773358a1b03e9
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2020-08-27 (Thu, 27 Aug 2020)

  Changed paths:
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/lib/CodeGen/CGCall.cpp
    M clang/lib/CodeGen/CGExprScalar.cpp
    M clang/lib/CodeGen/TargetInfo.cpp
    A clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
    A clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
    A clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
    A clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
    A clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
    A clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
    A clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
    A clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp

  Log Message:
  -----------
  [CodeGen][AArch64] Support arm_sve_vector_bits attribute

This patch implements codegen for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define vector-length-specific (VLS)
versions of existing vector-length-agnostic (VLA) types.

VLSTs are represented as VectorType in the AST and fixed-length vectors
in the IR everywhere except in function args/return. Implemented in this
patch is codegen support for the following:

  * Implicit casting between VLA <-> VLS types.
  * Coercion of VLS types in function args/return.
  * Mangling of VLS types.

Casting is handled by the CK_BitCast operation, which has been extended
to support the two new vector kinds for fixed-length SVE predicate and
data vectors, where the cast is implemented through memory rather than a
bitcast which is unsupported. Implementing this as a normal bitcast
would require relaxing checks in LLVM to allow bitcasting between
scalable and fixed types. Another option was adding target-specific
intrinsics, although codegen support would need to be added for these
intrinsics. Given this, casting through memory seemed like the best
approach as it's supported today and existing optimisations may remove
unnecessary loads/stores, although there is room for improvement here.

Coercion of VLSTs in function args/return from fixed to scalable is
implemented through the AArch64 ABI in TargetInfo.

The VLA and VLS types are defined by the ACLE to map to the same
machine-level SVE vectors. VLS types are mangled in the same way as:

  __SVE_VLS<typename, unsigned>

where the first argument is the underlying variable-length type and the
second argument is the SVE vector length in bits. For example:

  #if __ARM_FEATURE_SVE_BITS==512
  // Mangled as 9__SVE_VLSIu11__SVInt32_tLj512EE
  typedef svint32_t vec __attribute__((arm_sve_vector_bits(512)));
  // Mangled as 9__SVE_VLSIu10__SVBool_tLj512EE
  typedef svbool_t pred __attribute__((arm_sve_vector_bits(512)));
  #endif

The latest ACLE specification (00bet5) does not contain details of this
mangling scheme, it will be specified in the next revision.  The
mangling scheme is otherwise defined in the appendices to the Procedure
Call Standard for the Arm Architecture, see [2] for more information.

[1] https://developer.arm.com/documentation/100987/latest
[2] https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85743