[all-commits] [llvm/llvm-project] 23d5e9: [AArch64] Optimize instruction selection for certa...

[Mikhail Maltsev via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 23d5e93f342e168b59838476abc0e03853609617
      https://github.com/llvm/llvm-project/commit/23d5e93f342e168b59838476abc0e03853609617
  Author: Mikhail Maltsev <mikhail.maltsev at arm.com>
  Date:   2020-08-27 (Thu, 27 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
    M llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
    M llvm/test/CodeGen/AArch64/neon-extract.ll
    A llvm/test/CodeGen/AArch64/neon-wide-splat.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll

  Log Message:
  -----------
  [AArch64] Optimize instruction selection for certain vector shuffles

This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:
    shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
is essentially:
    shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D86225