[all-commits] [llvm/llvm-project] b7e359: [SelectionDAG] Handle non-power-of-2 bitwidths in ...

[jayfoad via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b7e3599a22a9fdea42bf40cae750d10a5fb56888
      https://github.com/llvm/llvm-project/commit/b7e3599a22a9fdea42bf40cae750d10a5fb56888
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2020-08-26 (Wed, 26 Aug 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    A llvm/test/CodeGen/WebAssembly/fshl.ll

  Log Message:
  -----------
  [SelectionDAG] Handle non-power-of-2 bitwidths in expandROT

Differential Revision: https://reviews.llvm.org/D86449