[all-commits] [llvm/llvm-project] e19ef1: [DSE, MemorySSA] Cache accesses with/without reacha...

[Florian Hahn via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e19ef1aab524ef10a2d118adcd9f6fd6ca2d7ca9
      https://github.com/llvm/llvm-project/commit/e19ef1aab524ef10a2d118adcd9f6fd6ca2d7ca9
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp

  Log Message:
  -----------
  [DSE,MemorySSA] Cache accesses with/without reachable read-clobbers.

Currently we repeatedly check the same uses for read clobbers in some
cases. We can avoid unnecessary checks by keeping track of the memory
accesses we already found read clobbers for. To do so, we just add
memory access causing read-clobbers to a set. Note that marking all
visited accesses as read-clobbers would be to pessimistic, as that might
include accesses not on any path to  the actual read clobber.

If we do not find any read-clobbers, we can add all visited instructions
to another set and use that to skip the same accesses in the next call.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D75025