[all-commits] [llvm/llvm-project] 116aff: TableGen/GlobalISel: Allow inst matcher to check m...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 116affb18dfc8c48ad0bd5134b42a51e34ad6fd8
      https://github.com/llvm/llvm-project/commit/116affb18dfc8c48ad0bd5134b42a51e34ad6fd8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-24 (Mon, 24 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Allow inst matcher to check multiple opcodes

This is to initially handleg immAllOnesV, which should match
G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be
used for other patterns cases that map to multiple G_* instructions,
such as G_ADD and G_PTR_ADD.