[all-commits] [llvm/llvm-project] 43465a: [LegalizeTypes][X86] Add ROTL/ROTR to WidenVectorR...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 43465a43755498e11b14ceb46e278bd127b3b3d7
      https://github.com/llvm/llvm-project/commit/43465a43755498e11b14ceb46e278bd127b3b3d7
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-08-24 (Mon, 24 Aug 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    A llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
    A llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll

  Log Message:
  -----------
  [LegalizeTypes][X86] Add ROTL/ROTR to WidenVectorResult.

We can widen these just like any other binary operation.

Added test cases for v2i32 for X86 for coverage.

Fixes failures seen after D77152.