[all-commits] [llvm/llvm-project] 41ba9d: [PowerPC] Support constrained vector fp/int conver...

[Qiu Chaofan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 41ba9d77231eac32f8a022eedffd261c47020dd4
      https://github.com/llvm/llvm-project/commit/41ba9d77231eac32f8a022eedffd261c47020dd4
  Author: Qiu Chaofan <qiucofan at cn.ibm.com>
  Date:   2020-08-24 (Mon, 24 Aug 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  Log Message:
  -----------
  [PowerPC] Support constrained vector fp/int conversion

This patch makes these operations legal, and add necessary codegen
patterns.

There's still some issue similar to D77033 for conversion from v1i128
type. But normal type tests synced in vector-constrained-fp-intrinsic
are passed successfully.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D83654