[all-commits] [llvm/llvm-project] 3f7985: [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler s...
dpreobra via All-commits
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Fri Aug 21 04:25:41 PDT 2020
Branch: refs/heads/master
Home: https://github.com/llvm/llvm-project
Commit: 3f7985e6ec21c21eb6d6cdd05ab206d0bcf2a770
https://github.com/llvm/llvm-project/commit/3f7985e6ec21c21eb6d6cdd05ab206d0bcf2a770
Author: Dmitry Preobrazhensky <dmitry.preobrazhensky at amd.com>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst
M llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
A llvm/docs/AMDGPU/gfx1011_src32_2.rst
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M llvm/docs/AMDGPU/gfx10_addr_mimg.rst
M llvm/docs/AMDGPU/gfx10_attr.rst
M llvm/docs/AMDGPU/gfx10_bimm16.rst
M llvm/docs/AMDGPU/gfx10_bimm32.rst
M llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
M llvm/docs/AMDGPU/gfx10_fimm16.rst
M llvm/docs/AMDGPU/gfx10_fimm32.rst
M llvm/docs/AMDGPU/gfx10_hwreg.rst
M llvm/docs/AMDGPU/gfx10_label.rst
M llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
M llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
M llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
M llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx10_opt.rst
M llvm/docs/AMDGPU/gfx10_param.rst
M llvm/docs/AMDGPU/gfx10_perm_smem.rst
M llvm/docs/AMDGPU/gfx10_ret.rst
M llvm/docs/AMDGPU/gfx10_sdata64_0.rst
M llvm/docs/AMDGPU/gfx10_sdst64_0.rst
M llvm/docs/AMDGPU/gfx10_sdst64_1.rst
M llvm/docs/AMDGPU/gfx10_simm16.rst
M llvm/docs/AMDGPU/gfx10_src32_1.rst
M llvm/docs/AMDGPU/gfx10_src32_2.rst
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M llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
M llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
M llvm/docs/AMDGPU/gfx10_tgt.rst
M llvm/docs/AMDGPU/gfx10_type_dev.rst
M llvm/docs/AMDGPU/gfx10_uimm16.rst
M llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
M llvm/docs/AMDGPU/gfx10_vcc_32.rst
M llvm/docs/AMDGPU/gfx10_waitcnt.rst
M llvm/docs/AMDGPU/gfx7_attr.rst
M llvm/docs/AMDGPU/gfx7_bimm16.rst
M llvm/docs/AMDGPU/gfx7_bimm32.rst
A llvm/docs/AMDGPU/gfx7_dst_buf_32.rst
M llvm/docs/AMDGPU/gfx7_fimm32.rst
M llvm/docs/AMDGPU/gfx7_hwreg.rst
M llvm/docs/AMDGPU/gfx7_label.rst
M llvm/docs/AMDGPU/gfx7_mod.rst
M llvm/docs/AMDGPU/gfx7_opt.rst
M llvm/docs/AMDGPU/gfx7_param.rst
M llvm/docs/AMDGPU/gfx7_ret.rst
M llvm/docs/AMDGPU/gfx7_simm16.rst
M llvm/docs/AMDGPU/gfx7_tgt.rst
M llvm/docs/AMDGPU/gfx7_type_dev.rst
M llvm/docs/AMDGPU/gfx7_uimm16.rst
M llvm/docs/AMDGPU/gfx7_waitcnt.rst
M llvm/docs/AMDGPU/gfx8_attr.rst
M llvm/docs/AMDGPU/gfx8_bimm16.rst
M llvm/docs/AMDGPU/gfx8_bimm32.rst
A llvm/docs/AMDGPU/gfx8_dst_buf_32.rst
M llvm/docs/AMDGPU/gfx8_fimm16.rst
M llvm/docs/AMDGPU/gfx8_fimm32.rst
M llvm/docs/AMDGPU/gfx8_hwreg.rst
M llvm/docs/AMDGPU/gfx8_imask.rst
M llvm/docs/AMDGPU/gfx8_label.rst
M llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
M llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
M llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx8_opt.rst
M llvm/docs/AMDGPU/gfx8_param.rst
M llvm/docs/AMDGPU/gfx8_perm_smem.rst
M llvm/docs/AMDGPU/gfx8_ret.rst
M llvm/docs/AMDGPU/gfx8_simm16.rst
M llvm/docs/AMDGPU/gfx8_src32_1.rst
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M llvm/docs/AMDGPU/gfx8_tgt.rst
M llvm/docs/AMDGPU/gfx8_type_dev.rst
M llvm/docs/AMDGPU/gfx8_uimm16.rst
M llvm/docs/AMDGPU/gfx8_waitcnt.rst
M llvm/docs/AMDGPU/gfx900_mad_type_dev.rst
M llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx900_src32_0.rst
M llvm/docs/AMDGPU/gfx900_src32_1.rst
M llvm/docs/AMDGPU/gfx904_mad_type_dev.rst
M llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx904_src32_0.rst
M llvm/docs/AMDGPU/gfx904_src32_1.rst
M llvm/docs/AMDGPU/gfx906_mad_type_dev.rst
M llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst
M llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst
M llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx906_src32_0.rst
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M llvm/docs/AMDGPU/gfx906_type_dev.rst
M llvm/docs/AMDGPU/gfx908_mad_type_dev.rst
M llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst
M llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst
M llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx908_offset_buf.rst
M llvm/docs/AMDGPU/gfx908_opt.rst
M llvm/docs/AMDGPU/gfx908_ret.rst
M llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst
M llvm/docs/AMDGPU/gfx908_src32_0.rst
M llvm/docs/AMDGPU/gfx908_src32_1.rst
M llvm/docs/AMDGPU/gfx908_src32_2.rst
M llvm/docs/AMDGPU/gfx908_src32_3.rst
A llvm/docs/AMDGPU/gfx908_src32_4.rst
A llvm/docs/AMDGPU/gfx908_src32_5.rst
M llvm/docs/AMDGPU/gfx908_type_dev.rst
M llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst
M llvm/docs/AMDGPU/gfx9_attr.rst
M llvm/docs/AMDGPU/gfx9_bimm16.rst
M llvm/docs/AMDGPU/gfx9_bimm32.rst
M llvm/docs/AMDGPU/gfx9_fimm16.rst
M llvm/docs/AMDGPU/gfx9_fimm32.rst
M llvm/docs/AMDGPU/gfx9_hwreg.rst
M llvm/docs/AMDGPU/gfx9_imask.rst
M llvm/docs/AMDGPU/gfx9_label.rst
M llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
M llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
M llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
M llvm/docs/AMDGPU/gfx9_opt.rst
M llvm/docs/AMDGPU/gfx9_param.rst
M llvm/docs/AMDGPU/gfx9_perm_smem.rst
M llvm/docs/AMDGPU/gfx9_ret.rst
M llvm/docs/AMDGPU/gfx9_simm16.rst
M llvm/docs/AMDGPU/gfx9_src32_1.rst
M llvm/docs/AMDGPU/gfx9_src32_2.rst
M llvm/docs/AMDGPU/gfx9_src32_3.rst
A llvm/docs/AMDGPU/gfx9_src32_4.rst
A llvm/docs/AMDGPU/gfx9_src32_5.rst
A llvm/docs/AMDGPU/gfx9_src32_6.rst
A llvm/docs/AMDGPU/gfx9_src32_7.rst
M llvm/docs/AMDGPU/gfx9_tgt.rst
M llvm/docs/AMDGPU/gfx9_type_dev.rst
M llvm/docs/AMDGPU/gfx9_uimm16.rst
M llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
M llvm/docs/AMDGPU/gfx9_waitcnt.rst
M llvm/docs/AMDGPUInstructionNotation.rst
M llvm/docs/AMDGPUInstructionSyntax.rst
M llvm/docs/AMDGPUModifierSyntax.rst
M llvm/docs/AMDGPUOperandSyntax.rst
Log Message:
-----------
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of MTBUF instructions and format modifier;
- described limitations of f16 inline constants when used with integer operands;
- updated description of gfx9+ flat global addressing modes;
- v_accvgpr_write_b32 src0 corrections (gfx908);
- minor bugfixing and improvements.
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