[all-commits] [llvm/llvm-project] df9a9b: [X86] Correct the implementation of the testFeatur...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: df9a9bb7beb7bc04ca4188fe0e527baac2900ff1
      https://github.com/llvm/llvm-project/commit/df9a9bb7beb7bc04ca4188fe0e527baac2900ff1
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-08-20 (Thu, 20 Aug 2020)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model.c

  Log Message:
  -----------
  [X86] Correct the implementation of the testFeature macro in getIntelProcessorTypeAndSubtype to do a proper bit test.

Instead of ANDing with a one hot mask representing the bit to
be tested, we were ANDing with just the bit number. This tests
multiple bits none of them the correct one.

This caused skylake-avx512, cascadelake and cooperlake to all
be misdetected. Based on experiments with the Intel SDE, it seems
that all of these CPUs are being detected as being cooperlake.
This is bad since its the newest CPU of the 3.