[all-commits] [llvm/llvm-project] 54d8de: allSGPRSpillsAreDead() should use actual FP/BP fra...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Thu Aug 20 13:17:06 PDT 2020


  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 54d8ded4b19aeba05006367766d148d34be01c02
      https://github.com/llvm/llvm-project/commit/54d8ded4b19aeba05006367766d148d34be01c02
  Author: vnalamot <VenkataRamanaiah.Nalamothu at amd.com>
  Date:   2020-08-20 (Thu, 20 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

  Log Message:
  -----------
  allSGPRSpillsAreDead() should use actual FP/BP frame indices

The SGPR spills happen in SILowerSGPRSpills() and allSGPRSpillsAreDead()
make sure there are no SGPR spills pending during PEI. But the FP/BP
spills happen during PEI and are exceptions.

Use actual frame indices of FP/BP in allSGPRSpillsAreDead() to
accommodate the exceptions.

Differential Revision: https://reviews.llvm.org/D86291


  Commit: 18b218007db69627bb651bb2a548afe92d615cd3
      https://github.com/llvm/llvm-project/commit/18b218007db69627bb651bb2a548afe92d615cd3
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-20 (Thu, 20 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Legalize odd sized loads with widening

Custom lower and widen odd sized loads up to the alignment. The
default set of legalization actions doesn't have a way to represent
this. This fixes naturally aligned <3 x s8> and <3 x s16> loads.

This also starts moving towards eliminating the buggy and
overcomplicated legalization rules for narrowing. All the memory size
changes should be done in the lower or custom action, not NarrowScalar
/ FewerElements. These currently have redundant and ambiguous code
with the lower action.


Compare: https://github.com/llvm/llvm-project/compare/b74b80bb2d31...18b218007db6


More information about the All-commits mailing list