[all-commits] [llvm/llvm-project] 3149ec: [RISCV] Enable MCCodeEmitter instruction predicate...

[Jessica Clarke via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3149ec07c0247397f7d963ccff28773a00bcdf9c
      https://github.com/llvm/llvm-project/commit/3149ec07c0247397f7d963ccff28773a00bcdf9c
  Author: Jessica Clarke <jrtc27 at jrtc27.com>
  Date:   2020-08-20 (Thu, 20 Aug 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

  Log Message:
  -----------
  [RISCV] Enable MCCodeEmitter instruction predicate verifier

This ensures that we never encode an instruction which is unavailable,
such as if we explicitly insert a forbidden instruction when lowering.
This is particularly important on RISC-V given its high degree of
modularity, and will become increasingly important as new standard
extensions appear.

Reviewed By: asb, lenary

Differential Revision: https://reviews.llvm.org/D85015