[all-commits] [llvm/llvm-project] 31adc2: GlobalISel: Implement fewerElementsVector for G_CO...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 31adc28d24b1a95bb47df23068b6f61dfb5cd012
      https://github.com/llvm/llvm-project/commit/31adc28d24b1a95bb47df23068b6f61dfb5cd012
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-19 (Wed, 19 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

  Log Message:
  -----------
  GlobalISel: Implement fewerElementsVector for G_CONCAT_VECTORS sources

This fixes <6 x s16> = G_CONCAT_VECTORS from <3 x s16> handling.