[all-commits] [llvm/llvm-project] e887d0: [AArch64][GlobalISel] Handle rtcGPR64RegClassID in...

[Raul Tambre via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e887d0e89b837be37b4279735a9c1ac57e90c995
      https://github.com/llvm/llvm-project/commit/e887d0e89b837be37b4279735a9c1ac57e90c995
  Author: Raul Tambre <raul at tambre.ee>
  Date:   2020-08-19 (Wed, 19 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()

TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16
and X17, as it's the last matching class. This in turn gets passed to
AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable.

It seems sensible to handle this case, so copies from X16 and X17 work.
Copying from X17 is used in inline assembly in libunwind for pointer
authentication.

Differential Revision: https://reviews.llvm.org/D85720