[all-commits] [llvm/llvm-project] 6c5039: [RISCV] add the assemble and disassemble support o...

[luxufan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c5039a10f339ecec1a6d342aa5b5721d12c3138
      https://github.com/llvm/llvm-project/commit/6c5039a10f339ecec1a6d342aa5b5721d12c3138
  Author: luxufan <932494295 at qq.com>
  Date:   2020-08-19 (Wed, 19 Aug 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket32.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket64.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    A llvm/test/MC/RISCV/rvv/zvlsseg.s

  Log Message:
  -----------
  [RISCV] add the assemble and disassemble support of Zvlsseg instructions

This implements the assemble and disassemble support of RISCV Vector
extension Zvlsseg instructions, base on the 0.9 spec version.

Reviewed  by HsiangKai

Differential Revision: https://reviews.llvm.org/D84416