[all-commits] [llvm/llvm-project] 347152: [ARM] Allow tail predication of VLDn

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3471520b1f6bc4fedfe45505f02924dc44e5106f
      https://github.com/llvm/llvm-project/commit/3471520b1f6bc4fedfe45505f02924dc44e5106f
  Author: David Green <david.green at arm.com>
  Date:   2020-08-18 (Tue, 18 Aug 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
    M llvm/unittests/Target/ARM/MachineInstrTest.cpp

  Log Message:
  -----------
  [ARM] Allow tail predication of VLDn

VLD2/4 instructions cannot be predicated, so we cannot tail predicate
them from autovec. From intrinsics though, they should be valid as they
will just end up loading extra values into off vector lanes, not
effecting the on lanes. The same is true for loads in general where so
long as we are not using the other vector lanes, an unpredicated load
can be converted to a predicated one.

This marks VLD2 and VLD4 instructions as validForTailPredication and
allows any unpredicated load in tail predication loop, which seems to be
valid given the other checks we have.

Differential Revision: https://reviews.llvm.org/D86022