[all-commits] [llvm/llvm-project] 9f63dc: [SVE] Fix shift-by-imm patterns used by asr, lsl &...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f63dc3265748bf63d7475ba4013dc1b0c728f6c
      https://github.com/llvm/llvm-project/commit/9f63dc3265748bf63d7475ba4013dc1b0c728f6c
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-08-18 (Tue, 18 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll

  Log Message:
  -----------
  [SVE] Fix shift-by-imm patterns used by asr, lsl & lsr intrinsics.

Right shift patterns will no longer incorrectly accept a shift
amount of zero.  At the same time they will allow larger shift
amounts that are now saturated to their upper bound.

Patterns have been extended to enable immediate forms for shifts
taking an arbitrary predicate.

This patch also unifies the code path for immediate parsing so the
i64 based shifts are no longer treated specially.

Differential Revision: https://reviews.llvm.org/D86084