[all-commits] [llvm/llvm-project] 3d0470: [AArch64][SVE] Fix CFA calculation in presence of ...

[David Blaikie via All-commits]

  Branch: refs/heads/release/11.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d0470ae802ae443a2df39f495d2ddd92805c8f8
      https://github.com/llvm/llvm-project/commit/3d0470ae802ae443a2df39f495d2ddd92805c8f8
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/include/llvm/MC/MCDwarf.h
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64StackOffset.h
    M llvm/test/CodeGen/AArch64/framelayout-sve.mir
    M llvm/test/CodeGen/AArch64/sve-trunc.ll

  Log Message:
  -----------
  [AArch64][SVE] Fix CFA calculation in presence of SVE objects.

The CFA is calculated as (SP/FP + offset), but when there are
SVE objects on the stack the SP offset is partly scalable and
should instead be expressed as the DWARF expression:

     SP + offset + scalable_offset * VG

where VG is the Vector Granule register, containing the
number of 64bits 'granules' in a scalable vector.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84043

(cherry picked from commit fd6584a22043b254a323635c142b28ce80ae5b5b)


  Commit: 8a755a4c3ee7738bbeea92829dfc2876445ff366
      https://github.com/llvm/llvm-project/commit/8a755a4c3ee7738bbeea92829dfc2876445ff366
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/test/CodeGen/AArch64/framelayout-sve.mir
    M llvm/test/CodeGen/AArch64/sve-trunc.ll

  Log Message:
  -----------
  [AArch64][SVE] Add missing unwind info for SVE registers.

This patch adds a CFI entry for each SVE callee saved register
that needs unwind info at an offset from the CFA. The offset is
a DWARF expression because the offset is partly scalable.

The CFI entries only cover a subset of the SVE callee-saves and
only encodes the lower 64-bits, thus implementing the lowest
common denominator ABI. Existing unwinders may support VG but
only restore the lower 64-bits.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84044

(cherry picked from commit bb3344c7d8c2703c910dd481ada43ecaf11536a6)


  Commit: d485dbdcd1e90dd0a715e78c6532227e7ed10e4d
      https://github.com/llvm/llvm-project/commit/d485dbdcd1e90dd0a715e78c6532227e7ed10e4d
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    A llvm/test/CodeGen/AArch64/sve-tailcall.ll

  Log Message:
  -----------
  [AArch64][SVE] Disable tail calls if callee does not preserve SVE regs.

This fixes an issue triggered by the following code, where emitEpilogue
got confused when trying to restore the SVE registers after the call,
whereas the call to bar() is implemented as a TCReturn:

  int non_sve();
  int sve(svint32_t x) { return non_sve(); }

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84869

(cherry picked from commit f2916636f83dfeb4808a16045db0025783743471)


  Commit: 2d52adc4ade0d194a3341742b01d088c5fdd70c6
      https://github.com/llvm/llvm-project/commit/2d52adc4ade0d194a3341742b01d088c5fdd70c6
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

  Log Message:
  -----------
  [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors

Fixed an incorrect pattern in lib/Target/AArch64/AArch64SVEInstrInfo.td
for storing out <vscale x 2 x f32> unpacked scalable vectors. Added
a couple of tests to

  test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

Differential Revision: https://reviews.llvm.org/D85441

(cherry picked from commit 0905d9f31ead399d054c5d2a2c353e690f5c8daa)


  Commit: a318950c0f9b166245b3d912be2642af7584a078
      https://github.com/llvm/llvm-project/commit/a318950c0f9b166245b3d912be2642af7584a078
  Author: David Blaikie <dblaikie at gmail.com>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

  Log Message:
  -----------
  Fix -Wconstant-conversion warning with explicit cast

Introduced by fd6584a22043b254a323635c142b28ce80ae5b5b

Following similar use of casts in AsmParser.cpp, for instance - ideally
this type would use unsigned chars as they're more representative of raw
data and don't get confused around implementation defined choices of
char's signedness, but this is what it is & the signed/unsigned
conversions are (so far as I understand) safe/bit preserving in this
usage and what's intended, given the API design here.

(cherry picked from commit e31cfc4cd3e393300002e9c519787c96e3b67bab)


Compare: https://github.com/llvm/llvm-project/compare/e6ec96f4215a...a318950c0f9b