[all-commits] [llvm/llvm-project] 79d9e2: [DemandedBits] Reorder addition test checks. NFC.

Simon Pilgrim via All-commits all-commits at lists.llvm.org
Mon Aug 17 04:57:16 PDT 2020


  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 79d9e2cd93a3ff7b448f40caf50dbfd3516f7c0d
      https://github.com/llvm/llvm-project/commit/79d9e2cd93a3ff7b448f40caf50dbfd3516f7c0d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/test/Analysis/DemandedBits/add.ll

  Log Message:
  -----------
  [DemandedBits] Reorder addition test checks. NFC.

As suggested on D72423 we should try to keep the same order as the original IR


  Commit: c1f6ce0c7322d47f1bb90169585fa54232231ede
      https://github.com/llvm/llvm-project/commit/c1f6ce0c7322d47f1bb90169585fa54232231ede
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-08-17 (Mon, 17 Aug 2020)

  Changed paths:
    M llvm/include/llvm/Analysis/DemandedBits.h
    M llvm/lib/Analysis/DemandedBits.cpp
    M llvm/test/Analysis/DemandedBits/add.ll
    M llvm/unittests/IR/CMakeLists.txt
    A llvm/unittests/IR/DemandedBitsTest.cpp
    M llvm/unittests/Support/KnownBitsTest.cpp
    A llvm/unittests/Support/KnownBitsTest.h

  Log Message:
  -----------
  [DemandedBits] Improve accuracy of Add propagator

The current demand propagator for addition will mark all input bits at and right of the alive output bit as alive. But carry won't propagate beyond a bit for which both operands are zero (or one/zero in the case of subtraction) so a more accurate answer is possible given known bits.

I derived a propagator by working through truth tables and using a bit-reversed addition to make demand ripple to the right, but I'm not sure how to make a convincing argument for its correctness in the comments yet. Nevertheless, here's a minimal implementation and test to get feedback.

This would help in a situation where, for example, four bytes (<128) packed into an int are added with four others SIMD-style but only one of the four results is actually read.

Known A:     0_______0_______0_______0_______
Known B:     0_______0_______0_______0_______
AOut:        00000000001000000000000000000000
AB, current: 00000000001111111111111111111111
AB, patch:   00000000001111111000000000000000

Committed on behalf of: @rrika (Erika)

Differential Revision: https://reviews.llvm.org/D72423


Compare: https://github.com/llvm/llvm-project/compare/613d8f29538e...c1f6ce0c7322


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