[all-commits] [llvm/llvm-project] c7a0b2: [X86][MC][Target] Initial backend support a tune C...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c7a0b2684f74de5ba725d984cacd151863f9f803
      https://github.com/llvm/llvm-project/commit/c7a0b2684f74de5ba725d984cacd151863f9f803
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-08-14 (Fri, 14 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
    M llvm/include/llvm/MC/MCSubtargetInfo.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/TargetSubtargetInfo.cpp
    M llvm/lib/MC/MCSubtargetInfo.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
    M llvm/lib/Target/AVR/AVRSubtarget.cpp
    M llvm/lib/Target/AVR/AVRSubtarget.h
    M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
    M llvm/lib/Target/BPF/BPFSubtarget.cpp
    M llvm/lib/Target/BPF/BPFSubtarget.h
    M llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
    M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
    M llvm/lib/Target/Hexagon/HexagonSubtarget.h
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
    M llvm/lib/Target/Lanai/LanaiSubtarget.cpp
    M llvm/lib/Target/Lanai/LanaiSubtarget.h
    M llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
    M llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
    M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
    M llvm/lib/Target/MSP430/MSP430Subtarget.h
    M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
    M llvm/lib/Target/Mips/MipsSubtarget.cpp
    M llvm/lib/Target/Mips/MipsSubtarget.h
    M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
    M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
    M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
    M llvm/lib/Target/PowerPC/PPCSubtarget.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
    M llvm/lib/Target/Sparc/SparcSubtarget.cpp
    M llvm/lib/Target/Sparc/SparcSubtarget.h
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
    M llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
    M llvm/lib/Target/SystemZ/SystemZSubtarget.h
    M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
    M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86Subtarget.cpp
    M llvm/lib/Target/X86/X86Subtarget.h
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
    M llvm/lib/Target/XCore/XCoreSubtarget.cpp
    M llvm/lib/Target/XCore/XCoreSubtarget.h
    M llvm/unittests/CodeGen/MFCommon.inc
    M llvm/utils/TableGen/SubtargetEmitter.cpp

  Log Message:
  -----------
  [X86][MC][Target] Initial backend support a tune CPU to support -mtune

This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line.

This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned.

One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU.

I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning.

Differential Revision: https://reviews.llvm.org/D85165