[all-commits] [llvm/llvm-project] 5c5e6d: TableGen/GlobalISel: Partially handle immAllOnesV/...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c5e6d951eec7ce89ed49f8220ce8442c1d20472
      https://github.com/llvm/llvm-project/commit/5c5e6d951eec7ce89ed49f8220ce8442c1d20472
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-14 (Fri, 14 Aug 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
    M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
    M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
    M llvm/lib/CodeGen/GlobalISel/Utils.cpp
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
    A llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV

These should really match either G_BUILD_VECTOR or
G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing
mechanism for matching alternative opcodes. There is GIM_SwitchOpcode,
but it seems to assume it's oly only used for matcher optimization.

I could also omit any opcode check and rely on the matcher directly
checking the opcode, but the table optimizer currently assumes there
has to be an opcode check.

Also doesn't try to handle undef elements like the DAG version.