[all-commits] [llvm/llvm-project] 40a142: AMDGPU/GlobalISel: Match andn2/orn2 for more types

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 40a142fa57d648e3daadfdaa75731360e1ebab2e
      https://github.com/llvm/llvm-project/commit/40a142fa57d648e3daadfdaa75731360e1ebab2e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-14 (Fri, 14 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Match andn2/orn2 for more types

Unfortunately this ends up not working as expected on targets with
16-bit operations due to AMDGPUCodeGenPrepare's promotion of uniform
16-bit ops to i32.

The vector case annoyingly requires switching the checked opcode,
since constants for vectors aren't directly handled.

I also need to think more carefully about whether this is valid for i1.