[all-commits] [llvm/llvm-project] 6af167: [SVE][CodeGen] Fix scalable vector issues in DAGTy...

[david-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6af1677161fbcdedf8ba08e8ffd065c9451ae733
      https://github.com/llvm/llvm-project/commit/6af1677161fbcdedf8ba08e8ffd065c9451ae733
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2020-08-13 (Thu, 13 Aug 2020)

  Changed paths:
    M llvm/include/llvm/Support/TypeSize.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

  Log Message:
  -----------
  [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorStores

In DAGTypeLegalizer::GenWidenVectorStores the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the main loop in
that function to use TypeSize instead of unsigned for tracking the
remaining store amount and offset increment. In addition, I've changed
the loop to use the new IncrementPointer helper function for updating
the addresses in each iteration, since this handles scalable vector
types.

Whilst fixing this function I also fixed a minor issue in
IncrementPointer whereby we were not adding the no-unsigned-wrap flag
for the add instruction in the same way as the fixed width case does.

Also, I've added a report_fatal_error in GenWidenVectorTruncStores,
since this code currently uses a sequence of element-by-element scalar
stores.

I've added new tests in

  CodeGen/AArch64/sve-intrinsics-stores.ll
  CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

for the changes in GenWidenVectorStores.

Differential Revision: https://reviews.llvm.org/D84937