[all-commits] [llvm/llvm-project] 23bd33: [InstCombine] prefer xor with -1 because 'not' is ...

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  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 23bd33c6acc4fa0ddc097d3d0767860cc014f6e0
      https://github.com/llvm/llvm-project/commit/23bd33c6acc4fa0ddc097d3d0767860cc014f6e0
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-08-12 (Wed, 12 Aug 2020)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/and-xor-or.ll
    M llvm/test/Transforms/InstCombine/or-xor.ll
    M llvm/test/Transforms/InstCombine/xor.ll

  Log Message:
  -----------
  [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)

This is a retry of rL300977 which was reverted because of infinite loops.
We have fixed all of the known places where that would happen, but there's
still a chance that this patch will cause infinite loops.

This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706

Differential Revision: https://reviews.llvm.org/D32255