[all-commits] [llvm/llvm-project] c561f4: [SVE][VLS] Don't combine logical AND.

[Francesco Petrogalli via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c561f4d2ec19667252c3429ba100c71d38fa3c1d
      https://github.com/llvm/llvm-project/commit/c561f4d2ec19667252c3429ba100c71d38fa3c1d
  Author: Francesco Petrogalli <francesco.petrogalli at arm.com>
  Date:   2020-08-12 (Wed, 12 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll

  Log Message:
  -----------
  [SVE][VLS] Don't combine logical AND.

Testing is performed when targeting 128, 256 and 512-bit wide vectors.

For 128-bit vectors, the original behavior of using NEON instructions is
preserved.

Differential Revision: https://reviews.llvm.org/D85479