[all-commits] [llvm/llvm-project] b0b95d: [VectorCombine] add safety check for 0-width register

[RotateRight via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b0b95dab1ce21d93f3d62bc37256da9f38cff616
      https://github.com/llvm/llvm-project/commit/b0b95dab1ce21d93f3d62bc37256da9f38cff616
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2020-08-11 (Tue, 11 Aug 2020)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VectorCombine.cpp

  Log Message:
  -----------
  [VectorCombine] add safety check for 0-width register

Based on post-commit discussion in D81766, Hexagon sets this to "0".
I'll see if I can come up with a test, but making the obvious
code fix first to unblock that target.