[all-commits] [llvm/llvm-project] f467b6: [Xtensa] Recognize Xtensa in triple parsing code.
Andrei Safronov via All-commits
all-commits at lists.llvm.org
Tue Aug 11 15:40:14 PDT 2020
Branch: refs/heads/xtensa_release_10.0.1
Home: https://github.com/llvm/llvm-project
Commit: f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3
https://github.com/llvm/llvm-project/commit/f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M llvm/include/llvm/ADT/Triple.h
M llvm/lib/Support/Triple.cpp
M llvm/unittests/ADT/TripleTest.cpp
Log Message:
-----------
[Xtensa] Recognize Xtensa in triple parsing code.
Commit: a5de2cb07ee51335238913565f9a58ed73f1bac8
https://github.com/llvm/llvm-project/commit/a5de2cb07ee51335238913565f9a58ed73f1bac8
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
A llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/module.modulemap
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/Object/obj2yaml.test
A llvm/test/tools/llvm-readobj/ELF/reloc-types-xtensa.test
Log Message:
-----------
[Xtensa] Add definitions and relocs for Xtensa ELF.
Commit: 82bd91c55a4374cbe11d171e1a25e84aa701791e
https://github.com/llvm/llvm-project/commit/82bd91c55a4374cbe11d171e1a25e84aa701791e
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/LLVMBuild.txt
A llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/LLVMBuild.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/LLVMBuild.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
A llvm/lib/Target/Xtensa/TargetInfo/CMakeLists.txt
A llvm/lib/Target/Xtensa/TargetInfo/LLVMBuild.txt
A llvm/lib/Target/Xtensa/TargetInfo/XtensaTargetInfo.cpp
A llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
A llvm/lib/Target/Xtensa/XtensaTargetMachine.h
Log Message:
-----------
[Xtensa] Add initial version of the Xtensa backend.
Commit: ae4dd5fc0aa67ff3b9a00fbc93a57ff1a7a8ad31
https://github.com/llvm/llvm-project/commit/ae4dd5fc0aa67ff3b9a00fbc93a57ff1a7a8ad31
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaInstrFormats.td
A llvm/lib/Target/Xtensa/XtensaInstrInfo.td
A llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
Log Message:
-----------
[Xtensa] Add basic *td files with Xtensa architecture
description.
Add Xtensa.td, XtensaInstrInfo.td etc. Currently add just part of Core
Instructions like ALU, processor control, memory barrier and some move
instructions. Add instructions formats and basic registers.
Commit: 31422c08942d68891dcc028a478e4beb19af6946
https://github.com/llvm/llvm-project/commit/31422c08942d68891dcc028a478e4beb19af6946
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.h
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaOperands.td
Log Message:
-----------
[Xtensa] Add Xtensa MCTargetDescr initial
functionality.
Add FDE CFI encoding for Xtensa.
Commit: 4a07a17a1bfa99dfc88753a6fee305e6532959ad
https://github.com/llvm/llvm-project/commit/4a07a17a1bfa99dfc88753a6fee305e6532959ad
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
A llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
A llvm/lib/Target/Xtensa/AsmParser/LLVMBuild.txt
A llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/LLVMBuild.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/Xtensa.td
Log Message:
-----------
[Xtensa] Add Xtensa basic assembler parser.
Commit: 34385c2abb851926b88160a10cf05792c255e20a
https://github.com/llvm/llvm-project/commit/34385c2abb851926b88160a10cf05792c255e20a
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/LLVMBuild.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/test/MC/Xtensa/elf-header.s
A llvm/test/MC/Xtensa/lit.local.cfg
A llvm/test/MC/Xtensa/xtensa-invalid.s
A llvm/test/MC/Xtensa/xtensa-valid.s
Log Message:
-----------
[Xtensa] Add basic Xtensa instruction printer.
Add instruction printer and basic tests of the
Xtensa instructions.
Commit: c6dce21897ec70408f4dc6f6e40a49550835308f
https://github.com/llvm/llvm-project/commit/c6dce21897ec70408f4dc6f6e40a49550835308f
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/test/MC/Xtensa/xtensa-invalid.s
M llvm/test/MC/Xtensa/xtensa-valid.s
Log Message:
-----------
[Xtensa] Add descriptions of the Xtensa
shift/load/store instructions.
Commit: f07fbd56c00c020e5ca1db11eeb5d561287446db
https://github.com/llvm/llvm-project/commit/f07fbd56c00c020e5ca1db11eeb5d561287446db
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
A llvm/lib/Target/Xtensa/Disassembler/LLVMBuild.txt
A llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/LLVMBuild.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaOperands.td
Log Message:
-----------
[Xtensa] Add basic support of Xtensa disassembler.
Commit: 52c60b8d91e95dec05bb0701b8c54ce0e1cec5cd
https://github.com/llvm/llvm-project/commit/52c60b8d91e95dec05bb0701b8c54ce0e1cec5cd
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/test/MC/Xtensa/fixups-diagnostics.s
A llvm/test/MC/Xtensa/fixups.s
A llvm/test/MC/Xtensa/relocations.s
M llvm/test/MC/Xtensa/xtensa-invalid.s
M llvm/test/MC/Xtensa/xtensa-valid.s
Log Message:
-----------
[Xtensa] Add support of the rest part of Xtensa Core
Instructions.
Add relocations and fixups support in object files generation.
Modify tests to support new instructions. Add tests for relocations
and fixups.
Commit: 033e45a8a8daf67efbd0985292e35551d83dd291
https://github.com/llvm/llvm-project/commit/033e45a8a8daf67efbd0985292e35551d83dd291
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/LLVMBuild.txt
A llvm/lib/Target/Xtensa/Xtensa.h
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
A llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
A llvm/lib/Target/Xtensa/XtensaCallingConv.td
A llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
A llvm/lib/Target/Xtensa/XtensaFrameLowering.h
A llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
A llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
A llvm/lib/Target/Xtensa/XtensaISelLowering.h
A llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
A llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
A llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
A llvm/lib/Target/Xtensa/XtensaMCInstLower.h
A llvm/lib/Target/Xtensa/XtensaOperators.td
A llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
A llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
A llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
A llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
Log Message:
-----------
[Xtensa] Initial codegen support for simple ALU operations.
Commit: 11f471988303a529ea0dbca706a9c7c27f49d47b
https://github.com/llvm/llvm-project/commit/11f471988303a529ea0dbca706a9c7c27f49d47b
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Log Message:
-----------
[Xtensa] Codegen support for memory operations
Commit: 1ade5a7d2b920756900291fca1e32b212a8c667c
https://github.com/llvm/llvm-project/commit/1ade5a7d2b920756900291fca1e32b212a8c667c
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
Log Message:
-----------
[Xtensa] Add Constant Pool
Commit: 5d977f2260f4f37b6da9e7727ca2106a64a27596
https://github.com/llvm/llvm-project/commit/5d977f2260f4f37b6da9e7727ca2106a64a27596
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
Log Message:
-----------
[Xtensa] Implement assembler representation of the Constant Pool.
Commit: b43a2047fe8b324ffea4475ecf3766e385d9e71c
https://github.com/llvm/llvm-project/commit/b43a2047fe8b324ffea4475ecf3766e385d9e71c
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Implement lowering constants.
Commit: eec02a020a38b00c391817ec0201736d7c40a20a
https://github.com/llvm/llvm-project/commit/eec02a020a38b00c391817ec0201736d7c40a20a
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.h
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
M llvm/lib/Target/Xtensa/XtensaMCInstLower.h
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
Log Message:
-----------
[Xtensa] Add support of the Xtensa function calls
Commit: 589caa8355460e2ce6acaf099e4d60c20d2faad8
https://github.com/llvm/llvm-project/commit/589caa8355460e2ce6acaf099e4d60c20d2faad8
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
M llvm/lib/Target/Xtensa/XtensaMCInstLower.h
Log Message:
-----------
[Xtensa] Implement lowering ConstantPool and address operations.
Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable.
Implement lowering of External and JumpTable symbols to MCInst
representation.
Commit: e88eeed4098c5f9d4812f151d9497743e24ea0a2
https://github.com/llvm/llvm-project/commit/e88eeed4098c5f9d4812f151d9497743e24ea0a2
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.h
Log Message:
-----------
[Xtensa] Implement emitPrologue/emitEpilogue
Commit: b59714cf3073caed500fd5a7f58f79b6bbd8611e
https://github.com/llvm/llvm-project/commit/b59714cf3073caed500fd5a7f58f79b6bbd8611e
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Implement lowering of dynamic_stackalloc, stacksave, stackrestore.
Commit: 59b0db8410fa4d17d8d09efcb5692779807f8f02
https://github.com/llvm/llvm-project/commit/59b0db8410fa4d17d8d09efcb5692779807f8f02
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
Log Message:
-----------
[Xtensa] Implement lowering SELECT_CC, SETCC
Commit: 3bf30d7db4a55dbca8981d78969f9e8045fe75e1
https://github.com/llvm/llvm-project/commit/3bf30d7db4a55dbca8981d78969f9e8045fe75e1
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Log Message:
-----------
[Xtensa] Support for a variety of additional LLVM IR constructs.
Commit: 38a38fdf8ed8a1ad5784b7603c01b8ff9b4f5a85
https://github.com/llvm/llvm-project/commit/38a38fdf8ed8a1ad5784b7603c01b8ff9b4f5a85
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
Log Message:
-----------
[Xtensa] Lower SHIFT PARTS and shift operations.
Also lower SHL, SRA, SRL with register operands.
Commit: 1a44f78aad94b8bc62e276b2b71e04fa1758b71c
https://github.com/llvm/llvm-project/commit/1a44f78aad94b8bc62e276b2b71e04fa1758b71c
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
Log Message:
-----------
[Xtensa] Implement load pseudo operations and patterns.
Implement load unsigned 8-bit pseudo operation. Implement
extending loads patterns extloadi1/i8/i16.
Commit: d8c569fbb2f5f62382d78b883c50f604498bcfb8
https://github.com/llvm/llvm-project/commit/d8c569fbb2f5f62382d78b883c50f604498bcfb8
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.cpp
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
Log Message:
-----------
[Xtensa] Support for variable arguments
Commit: 37ee475c16c4637f851d234dc419d64f2301ccf2
https://github.com/llvm/llvm-project/commit/37ee475c16c4637f851d234dc419d64f2301ccf2
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
Log Message:
-----------
[Xtensa] Implement lowering BR_JT operation
Commit: 7bb65f8ba3dec8f57579038326835bc5422a24ac
https://github.com/llvm/llvm-project/commit/7bb65f8ba3dec8f57579038326835bc5422a24ac
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Add support for llvm.{frameaddress,returnaddress} intrinsics.
Commit: 7ad70fe7ac9d483ec02d792f72158080a04c71c4
https://github.com/llvm/llvm-project/commit/7ad70fe7ac9d483ec02d792f72158080a04c71c4
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Add basic support for inline asm constraints
Commit: 9c8c53f539198fe8274d06cb85e3a44d50a9beb5
https://github.com/llvm/llvm-project/commit/9c8c53f539198fe8274d06cb85e3a44d50a9beb5
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
Log Message:
-----------
[Xtensa] Implement load/store from/to volatile memory location.
Commit: 7e41ba28bcc2d108c2836543f7c15ad6f80cd11e
https://github.com/llvm/llvm-project/commit/7e41ba28bcc2d108c2836543f7c15ad6f80cd11e
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
Log Message:
-----------
[Xtensa] Implement branch analysis
Commit: 98308c7cf4a2f6798d614981ff516ad6384418b5
https://github.com/llvm/llvm-project/commit/98308c7cf4a2f6798d614981ff516ad6384418b5
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
Log Message:
-----------
[Xtensa] Implement support for the BranchRelaxation
Commit: 985b48a393b91b5bec3f60e5bbc37803051b0b69
https://github.com/llvm/llvm-project/commit/985b48a393b91b5bec3f60e5bbc37803051b0b69
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
Log Message:
-----------
[Xtensa] Implement code density feature operations
Commit: e13b8cbd906958ffaeac5f8cc74bbd193e58b055
https://github.com/llvm/llvm-project/commit/e13b8cbd906958ffaeac5f8cc74bbd193e58b055
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/Xtensa.h
A llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
Log Message:
-----------
[Xtensa] Add code size reduction pass.
Commit: f284d22098ed7dda9119383faa5d0fcae309c18a
https://github.com/llvm/llvm-project/commit/f284d22098ed7dda9119383faa5d0fcae309c18a
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSizeReductionPass.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
Log Message:
-----------
[Xtensa] Implement Windowed feature operations.
Commit: 2e219b59c3a28354de7219ab1df60c4d142f49dd
https://github.com/llvm/llvm-project/commit/2e219b59c3a28354de7219ab1df60c4d142f49dd
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaCallingConv.td
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
Log Message:
-----------
[Xtensa] Implement Windowed Call ABI
Commit: dbba91813354fce62c304850e592ec2918ac8ff5
https://github.com/llvm/llvm-project/commit/dbba91813354fce62c304850e592ec2918ac8ff5
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.h
Log Message:
-----------
[Xtensa] Reserve an emergency spill slot for scavenger.
Reserve an emergency spill slot for the register scavenger
when Windowed Call ABI is used.
Commit: a1b1044e66d62f87658fa9f61fd9e79a8237f9ea
https://github.com/llvm/llvm-project/commit/a1b1044e66d62f87658fa9f61fd9e79a8237f9ea
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
Log Message:
-----------
[Xtensa] Implement Boolean feature operations
Commit: 52fafb49ae9afca9f8c39f5db4be694ecc6b7a7f
https://github.com/llvm/llvm-project/commit/52fafb49ae9afca9f8c39f5db4be694ecc6b7a7f
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
Log Message:
-----------
[Xtensa] Implement Floating-Point feature operations.
Also implement User Registers class.
Commit: b2fc3a5ad4943d1f99085c93516910c8020ee6ed
https://github.com/llvm/llvm-project/commit/b2fc3a5ad4943d1f99085c93516910c8020ee6ed
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
Log Message:
-----------
[Xtensa] Lowering Floating-Point Operations SELECT_CC/SETCC/BR_CC.
Implement DAG Combine for BRCOND operation with f32 operands.
Commit: 9cdcf2123a5d1d3ce74c57e402d5fe9c29e285ad
https://github.com/llvm/llvm-project/commit/9cdcf2123a5d1d3ce74c57e402d5fe9c29e285ad
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Implement DAG Combine for FADD and FSUB operations.
Commit: b6bfb8525b381e4201e887d3741a27aee428d706
https://github.com/llvm/llvm-project/commit/b6bfb8525b381e4201e887d3741a27aee428d706
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
Log Message:
-----------
[Xtensa] Implement Loop, SEXT and NSA features.
Commit: 10ab5e7454bb160833d79fb0eb4279029c1ec788
https://github.com/llvm/llvm-project/commit/10ab5e7454bb160833d79fb0eb4279029c1ec788
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
Log Message:
-----------
[Xtensa] Implement Mul32, Mul32High and Div32 features.
Commit: 0899e1af58463e88ceb7372929d9a57270474ecc
https://github.com/llvm/llvm-project/commit/0899e1af58463e88ceb7372929d9a57270474ecc
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/MC/Xtensa/xtensa-valid-mac16.s
Log Message:
-----------
[Xtensa] Implement Mac16 feature and operations.
Commit: 7652f90f25a11a939ad84be1f4ff4e6e589342d0
https://github.com/llvm/llvm-project/commit/7652f90f25a11a939ad84be1f4ff4e6e589342d0
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/MC/Xtensa/xtensa-valid-dbg.s
Log Message:
-----------
[Xtensa] Implement Xtensa features and operations.
Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features.
Commit: e11ae721f3da5121e1534c579ec54ab082d8ce76
https://github.com/llvm/llvm-project/commit/e11ae721f3da5121e1534c579ec54ab082d8ce76
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/MC/Xtensa/xtensa-valid-exc.s
A llvm/test/MC/Xtensa/xtensa-valid-int.s
A llvm/test/MC/Xtensa/xtensa-valid-regprotect.s
Log Message:
-----------
[Xtensa] Implement Xtensa features and operations.
Implement Exception, HighPriInterrupts, Coprocessor, Interrupt,
RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR
features. Implement instructions for Exception, Interrupt and
RegionProtection features with tests.
Commit: b58843feee726f55815fc3b168d9dfc91ababa0b
https://github.com/llvm/llvm-project/commit/b58843feee726f55815fc3b168d9dfc91ababa0b
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/Targets.cpp
A clang/lib/Basic/Targets/Xtensa.cpp
A clang/lib/Basic/Targets/Xtensa.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
Log Message:
-----------
[Xtensa] Add the Xtensa target.
Commit: e45d096c761df6c48936810106e43ed2a63cadce
https://github.com/llvm/llvm-project/commit/e45d096c761df6c48936810106e43ed2a63cadce
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M clang/lib/CodeGen/TargetInfo.cpp
Log Message:
-----------
[Xtensa] Implement Xtensa ABI lowering.
Commit: d95b4479fa1cc34d48b1744117b7b60d1a7cf671
https://github.com/llvm/llvm-project/commit/d95b4479fa1cc34d48b1744117b7b60d1a7cf671
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
Log Message:
-----------
[Xtensa] Add subtargets ESP32. ESP8266 and ESP32-S2.
Make ESP32 default subtarget.
Commit: a59c60ee15d7fb04a7a658cc7bb9ad1c1b07b371
https://github.com/llvm/llvm-project/commit/a59c60ee15d7fb04a7a658cc7bb9ad1c1b07b371
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M clang/lib/Basic/Targets/Xtensa.h
Log Message:
-----------
[Xtensa] Add esp32, esp8266 and esp32-s2 to valid cpu names.
Commit: add7649b2ba8c4866bde75ad0912180f4ef31857
https://github.com/llvm/llvm-project/commit/add7649b2ba8c4866bde75ad0912180f4ef31857
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
A llvm/test/MC/Xtensa/xtensa-valid-ur.s
M llvm/test/MC/Xtensa/xtensa-valid.s
Log Message:
-----------
[Xtensa] Improve parsing of the SR and UR registers.
Implement subtarget dependent SR and UR register parsing and
disassembling, add tests. Implement User Registers read/write
instructions adn add tests.
Commit: 57277fe27c0d9286fdc65ec539efa5a81860de4b
https://github.com/llvm/llvm-project/commit/57277fe27c0d9286fdc65ec539efa5a81860de4b
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
Log Message:
-----------
[Xtensa] Implement Xtensa specific streamer to support emit literals.
Commit: c74908ff62fea78f864a54d1bbd4f593e3375544
https://github.com/llvm/llvm-project/commit/c74908ff62fea78f864a54d1bbd4f593e3375544
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/test/MC/Xtensa/xtensa-invalid.s
Log Message:
-----------
[Xtensa] Improve assembler parsing. Improve CFA support.
Implement special processing of MOVI and L32R instructions in assembler
parser. The MOVI assembler expression now can have 32-bit immediate
values, so also correct xtensa-invalid.s test.
Also implement computation of CFA during XtensaMCAsmInfo creation.
Commit: 681236345a7156cc876f38ee7ca05f1433519281
https://github.com/llvm/llvm-project/commit/681236345a7156cc876f38ee7ca05f1433519281
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
Log Message:
-----------
[Xtensa] Lowering Exception Selector and Pointer Registers.
Commit: 3ee8b80290d4b8c08ef4ca3195e6663f1fd5bf14
https://github.com/llvm/llvm-project/commit/3ee8b80290d4b8c08ef4ca3195e6663f1fd5bf14
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
Log Message:
-----------
[Xtensa] Lowering GLobalTLSAddress operation.
Commit: 9042b744a7869393f361259fe610c123330838ad
https://github.com/llvm/llvm-project/commit/9042b744a7869393f361259fe610c123330838ad
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
Log Message:
-----------
[Xtensa] Lower ATOMIC_FENCE. Add Atomic Expand pass.
Commit: 89a7337aa91e632bc986c2330b3d311c17616d11
https://github.com/llvm/llvm-project/commit/89a7337aa91e632bc986c2330b3d311c17616d11
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
Log Message:
-----------
[Xtensa] Lower atomic_cmp_swap_(8/16/32) operations.
Commit: 242ed157c033b8735b67a20d9435a90492cc10b7
https://github.com/llvm/llvm-project/commit/242ed157c033b8735b67a20d9435a90492cc10b7
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
Log Message:
-----------
[Xtensa] Lower atomic_swap_(8/16/32) operations.
Commit: a8f41d4f14de71e14d6df5d4f4fa9381d74524ae
https://github.com/llvm/llvm-project/commit/a8f41d4f14de71e14d6df5d4f4fa9381d74524ae
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-21 (Tue, 21 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
Log Message:
-----------
[Xtensa] Lower atomic operations.
Commit: 3e307f980a3f886670dc2fc9d36e5238cf7accee
https://github.com/llvm/llvm-project/commit/3e307f980a3f886670dc2fc9d36e5238cf7accee
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-30 (Thu, 30 Jul 2020)
Changed paths:
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
A clang/lib/Driver/ToolChains/Xtensa.cpp
A clang/lib/Driver/ToolChains/Xtensa.h
Log Message:
-----------
[Xtensa] Implement Xtensa toolchain.
Commit: 22378fe217169cab332daa13c112c9823907e87e
https://github.com/llvm/llvm-project/commit/22378fe217169cab332daa13c112c9823907e87e
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-30 (Thu, 30 Jul 2020)
Changed paths:
A clang/include/clang/Basic/BuiltinsXtensa.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Basic/Targets/Xtensa.cpp
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/Sema/SemaChecking.cpp
M llvm/include/llvm/IR/CMakeLists.txt
M llvm/include/llvm/IR/Intrinsics.td
A llvm/include/llvm/IR/IntrinsicsXtensa.td
M llvm/lib/IR/Function.cpp
M llvm/lib/Target/Xtensa/XtensaDSPInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
A llvm/test/CodeGen/Xtensa/lit.local.cfg
A llvm/test/CodeGen/Xtensa/mac16_intrinsics.ll
M llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
Log Message:
-----------
[Xtensa] Implemented builtins for Xtensa MAC16 instructions.
Commit: 6fbc60664a7a6c63451d7c64b2963cf616635143
https://github.com/llvm/llvm-project/commit/6fbc60664a7a6c63451d7c64b2963cf616635143
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-30 (Thu, 30 Jul 2020)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
A llvm/test/CodeGen/Xtensa/funnel-shift.ll
Log Message:
-----------
[Xtensa] Implement lowering llvm intrinsics fshr/fshl.
Commit: 713f3bf47aea13c2a390332eb6d4db9ec853ef43
https://github.com/llvm/llvm-project/commit/713f3bf47aea13c2a390332eb6d4db9ec853ef43
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-07-30 (Thu, 30 Jul 2020)
Changed paths:
A .gitlab-ci.yml
Log Message:
-----------
Add .gitlab-ci.yml to support CI/CD
Commit: 1659ba158c4af4aacf1d331c33ebb7274c55386d
https://github.com/llvm/llvm-project/commit/1659ba158c4af4aacf1d331c33ebb7274c55386d
Author: Andrei Safronov <safronov at espressif.com>
Date: 2020-08-03 (Mon, 03 Aug 2020)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/TargetInfo/XtensaTargetInfo.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
Log Message:
-----------
[Xtensa] Correct visibility of the Xtensa backend initialize functions.
Make backend initialize functions public and visible outside library.
Closes #31
Compare: https://github.com/llvm/llvm-project/compare/f467b6ae0491%5E...1659ba158c4a
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