[all-commits] [llvm/llvm-project] 53f21e: TableGen/GlobalISel: Hack the operand order for at...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 53f21e0fb754799fc9a7ad7243a9161e2411b51d
      https://github.com/llvm/llvm-project/commit/53f21e0fb754799fc9a7ad7243a9161e2411b51d
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-11 (Tue, 11 Aug 2020)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
    A llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen/GlobalISel: Hack the operand order for atomic_store

ISD::ATOMIC_STORE arbitrarily has the operands in the opposite order
from regular ISD::STORE, which always introduced an annoying
duplication of patterns to handle both cases. Since in GlobalISel
there's just the one G_STORE, we need to swap the operands to
correctly emit the type check for the pointer operand.

Some work started in 20aafa31569b5157e792daa8860d71dd0df8a53a to
migrate SelectionDAG to use ISD::STORE for atomics, but that work
seems to have stalled. Since this is the pretty much the last
operation which matters which isn't supported for AMDGPU, use this
compatibility hack to unblock declaring it functionally complete.

Not sure what's going on with the pending_phis AArch64 test. It seems
it didn't always use atomics, and I'm not sure what it was originally
testing matters anymore.