[all-commits] [llvm/llvm-project] b6c7b7: [SVE] Add ISD nodes for predicated integer extend ...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b6c7b7fa31b738d97181416f06bbcc3dc5905407
      https://github.com/llvm/llvm-project/commit/b6c7b7fa31b738d97181416f06bbcc3dc5905407
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-08-11 (Tue, 11 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td

  Log Message:
  -----------
  [SVE] Add ISD nodes for predicated integer extend inreg operations.

These are useful instructions when lowering fixed length vector
extends, so I've broken this patch out as kind of NFC like work.

Differential Revision: https://reviews.llvm.org/D85546