[all-commits] [llvm/llvm-project] dbcfbf: [PowerPC] Add intrinsic to read or set FPSCR register

[Qiu Chaofan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: dbcfbffc7ae46cc7b84257787681676144a1bd5f
      https://github.com/llvm/llvm-project/commit/dbcfbffc7ae46cc7b84257787681676144a1bd5f
  Author: Qiu Chaofan <qiucofan at cn.ibm.com>
  Date:   2020-08-10 (Mon, 10 Aug 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsPowerPC.td
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
    A llvm/test/CodeGen/PowerPC/read-set-flm.ll

  Log Message:
  -----------
  [PowerPC] Add intrinsic to read or set FPSCR register

This patch introduces two intrinsics: llvm.ppc.setflm and
llvm.ppc.readflm. They read from or write to FPSCR register
(floating-point status & control) which contains rounding mode and
exception status.

To ensure correctness of program, we need to prevent FP operations from
being moved across these intrinsics (mffs/mtfsf instruction), so here I
set them as scheduling boundaries. We can relax such restriction if
FPSCR is modeled well in the future.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D84914