[all-commits] [llvm/llvm-project] 34040a: GlobalISel: Define InvalidRegBankID enum value

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 34040a4f61fecaa8e901ca2e5e587df13d7097ac
      https://github.com/llvm/llvm-project/commit/34040a4f61fecaa8e901ca2e5e587df13d7097ac
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-06 (Thu, 06 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/utils/TableGen/RegisterBankEmitter.cpp

  Log Message:
  -----------
  GlobalISel: Define InvalidRegBankID enum value


  Commit: 56270d1d421e00c98be169d9734c84350660781c
      https://github.com/llvm/llvm-project/commit/56270d1d421e00c98be169d9734c84350660781c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-08-06 (Thu, 06 Aug 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Start trying to handle AGPR bank

Try to use AGPR banks for the various merge/unmerge type
operations. Previously these would introduce copies to VGPR.


Compare: https://github.com/llvm/llvm-project/compare/8d072a440521...56270d1d421e