[all-commits] [llvm/llvm-project] 393799: [mlir] [VectorOps] Add masked load/store operation...

[Aart Bik via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 39379916a7f01d907562c1b70114568dac1778a2
      https://github.com/llvm/llvm-project/commit/39379916a7f01d907562c1b70114568dac1778a2
  Author: aartbik <ajcbik at google.com>
  Date:   2020-08-05 (Wed, 05 Aug 2020)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    A mlir/integration_test/Dialect/Vector/CPU/test-maskedload.mlir
    A mlir/integration_test/Dialect/Vector/CPU/test-maskedstore.mlir
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir] [VectorOps] Add masked load/store operations to Vector dialect

The intrinsics were already supported and vector.transfer_read/write lowered
direclty into these operations. By providing them as individual ops, however,
clients can used them directly, and it opens up progressively lowering transfer
operations at higher levels (rather than direct lowering to LLVM IR as done now).

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D85357