[all-commits] [llvm/llvm-project] 99a971: [X86][SSE] Start shuffle combining from ANY_EXTEND...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 99a971cadff7832a846394462c39a74aac64325d
      https://github.com/llvm/llvm-project/commit/99a971cadff7832a846394462c39a74aac64325d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/combine-pmuldq.ll
    M llvm/test/CodeGen/X86/mulvi32.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/promote-cmp.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
    M llvm/test/CodeGen/X86/vector-mul.ll
    M llvm/test/CodeGen/X86/vector-reduce-mul.ll
    M llvm/test/CodeGen/X86/vector-trunc-math.ll

  Log Message:
  -----------
  [X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets

We already do this on AVX (+ for ZERO_EXTEND_VECTOR_INREG), but this enables it for all SSE targets - we attempted something similar back at rL357057 but hit issues with the ZERO_EXTEND_VECTOR_INREG handling (PR41249).

I'm still looking at the vector-mul.ll regression - which is due to 32-bit targets performing the load as a f64, resulting in the shuffle combiner thinking it has to create a shuffle in the float domain.