[all-commits] [llvm/llvm-project] fd69df: [ARM] Distribute post-inc for Thumb2 sign/zero ext...

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fd69df62ed1091f25ba4749cc5152e9ce2fe3af4
      https://github.com/llvm/llvm-project/commit/fd69df62ed1091f25ba4749cc5152e9ce2fe3af4
  Author: David Green <david.green at arm.com>
  Date:   2020-08-01 (Sat, 01 Aug 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
    M llvm/test/CodeGen/Thumb2/postinc-distribute.mir

  Log Message:
  -----------
  [ARM] Distribute post-inc for Thumb2 sign/zero extending loads/stores

This adds sign/zero extending scalar loads/stores to the MVE
instructions added in D77813, allowing us to create up more post-inc
instructions. These are comparatively simple, compared to LDR/STR (which
may be better turned into an LDRD/LDM), but still require some additions
over MVE instructions. Because there are i12 and i8 variants of the
offset loads/stores dealing with different signs, we may need to convert
an i12 address to a i8 negative instruction. t2LDRBi12 can also be
shrunk to a tLDRi under the right conditions, so we need to be careful
with codesize too.

Differential Revision: https://reviews.llvm.org/D78625