[all-commits] [llvm/llvm-project] 66d60e: AMDGPU: Serialize MFI spill fields

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 66d60e06cbc51b453f9e38ad69795f9487213fe5
      https://github.com/llvm/llvm-project/commit/66d60e06cbc51b453f9e38ad69795f9487213fe5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-28 (Tue, 28 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll

  Log Message:
  -----------
  AMDGPU: Serialize MFI spill fields

These should probably be inferred from the function on parse, but the
target specific infrastructure currently does not give you a way to do
this. SILowerSGPRSpills early exits without this reporting spills,
which makes it difficult to write a MIR test for.


  Commit: 592f2e8d1ceb8ecec6f8b54eeb9fd7e0a099c0fe
      https://github.com/llvm/llvm-project/commit/592f2e8d1ceb8ecec6f8b54eeb9fd7e0a099c0fe
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-28 (Tue, 28 Jul 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    A llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir

  Log Message:
  -----------
  AMDGPU: Fix verifier error on spilling partially defined SGPRs

This needs an implicit def of the super-register in case one of the
lanes isn't defined, similar to copyPhysReg (or the not-VGPR spill
case below). This showed up in GlobalISel testing since it currently
doesn't fold out many undef instructions.


Compare: https://github.com/llvm/llvm-project/compare/fb22678cd678...592f2e8d1ceb