[all-commits] [llvm/llvm-project] a0ebac: [X86] Properly encode a 32-bit address with an ind...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a0ebac52df6d890fcba52e7db9ac66d0fc7c2582
      https://github.com/llvm/llvm-project/commit/a0ebac52df6d890fcba52e7db9ac66d0fc7c2582
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-27 (Mon, 27 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    M llvm/test/MC/X86/code16gcc.s

  Log Message:
  -----------
  [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode.

In 16-bit mode we can encode a 32-bit address using 0x67 prefix.
We were failing to do this when the index register was a 32-bit
register, the base register was not present, and the displacement
fit in 16-bits.

Fixes PR46866.


  Commit: 25f193fb46dbdcc178946765aa929535199e2a4b
      https://github.com/llvm/llvm-project/commit/25f193fb46dbdcc178946765aa929535199e2a4b
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-27 (Mon, 27 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/test/MC/X86/x86-16.s
    M llvm/test/MC/X86/x86-32.s

  Log Message:
  -----------
  [X86] Add support for {disp32} to control size of jmp and jcc instructions in the assembler

By default we pick a 1 byte displacement and let relaxation enlarge it if necessary. The GNU assembler supports a pseudo prefix to basically pre-relax the instruction the larger size.

I plan to add {disp8} and {disp32} support for memory operands in another patch which is why I've included the parsing code and enum for {disp8} pseudo prefix as well.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D84709


  Commit: 647e861e080382593648b234668ad2f5a376ac5e
      https://github.com/llvm/llvm-project/commit/647e861e080382593648b234668ad2f5a376ac5e
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-27 (Mon, 27 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/test/CodeGen/X86/pr46827.ll

  Log Message:
  -----------
  [X86] Detect if EFLAGs is live across XBEGIN pseudo instruction. Add it as livein to the basic blocks created when expanding the pseudo

XBEGIN causes several based blocks to be inserted. If flags are live across it we need to make eflags live in the new basic blocks to avoid machine verifier errors.

Fixes PR46827

Reviewed By: ivanbaev

Differential Revision: https://reviews.llvm.org/D84479


Compare: https://github.com/llvm/llvm-project/compare/a23f62343cb7...647e861e0803