[all-commits] [llvm/llvm-project] 930fc0: TableGen: Check if pattern outputs matches instruc...

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 930fc0b300b01890d3cafabfa85a8a50b2ca890e
      https://github.com/llvm/llvm-project/commit/930fc0b300b01890d3cafabfa85a8a50b2ca890e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-07-27 (Mon, 27 Jul 2020)

  Changed paths:
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  TableGen: Check if pattern outputs matches instruction defs

Attempt to fix address sanitizer bots when building ARM.