[all-commits] [llvm/llvm-project] df1252: [X86] Turn X86DAGToDAGISel::tryVPTERNLOG into a fu...

[topperc via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: df12524e6ba02d3eda975de4541f55e151074b07
      https://github.com/llvm/llvm-project/commit/df12524e6ba02d3eda975de4541f55e151074b07
  Author: Craig Topper <craig.topper at intel.com>
  Date:   2020-07-26 (Sun, 26 Jul 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/test/CodeGen/X86/avx512-logic.ll
    M llvm/test/CodeGen/X86/avx512vl-logic.ll

  Log Message:
  -----------
  [X86] Turn X86DAGToDAGISel::tryVPTERNLOG into a fully custom instruction selector that can handle bitcasts between logic ops

Previously we just matched the logic ops and replaced with an
X86ISD::VPTERNLOG node that we would send through the normal
pattern match. But that approach couldn't handle a bitcast
between the logic ops. Extending that approach would require us
to peek through the bitcasts and emit new bitcasts to match
the types. Those new bitcasts would then have to be properly
topologically sorted.

This patch instead switches to directly emitting the
MachineSDNode and skips the normal tablegen pattern matching.
We do have to handle load folding and broadcast load folding
ourselves now. Which also means commuting the immediate control.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D83630