[all-commits] [llvm/llvm-project] 3da1a9: [Statepoints] Support lowering gc relocations to v...

[Philip Reames via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 3da1a9634eb9d92b5ffa2571215c350a9641d07b
      https://github.com/llvm/llvm-project/commit/3da1a9634eb9d92b5ffa2571215c350a9641d07b
  Author: Philip Reames <listmail at philipreames.com>
  Date:   2020-07-25 (Sat, 25 Jul 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
    M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.h
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    A llvm/test/CodeGen/X86/statepoint-vreg.ll

  Log Message:
  -----------
  [Statepoints] Support lowering gc relocations to virtual registers

(Disabled under flag for the moment)

This is part of a larger project wherein we are finally integrating lowering of gc live operands with the register allocator.  Today, we force spill all operands in SelectionDAG.  The code to do so is distinctly non-optimal.  The approach this patch is working towards is to instead lower the relocations directly into the MI form, and let the register allocator pick which ones get spilled and which stack slots they get spilled to.  In terms of performance, the later part is actually more important as it avoids redundant shuffling of values between stack slots.

This particular change adds ISEL support to produce the variadic def STATEPOINT form required by the above.  In particular, the first N are lowered to variadic tied def/use pairs.  So new statepoint looks like this:
reloc1,reloc2,... = STATEPOINT ..., base1, derived1<tied-def0>, base2, derived2<tied-def1>, ...

N is limited by the maximal number of tied registers machine instruction can have (15 at the moment).

The current patch is restricted to handling relocations within a single basic block.  Cross block relocations (e.g. invokes) are handled via the legacy mechanism.  This restriction will be relaxed in future patches.

Patch By: dantrushin
Differential Revision: https://reviews.llvm.org/D81648