[all-commits] [llvm/llvm-project] 1dc1a3: [PowerPC] Implement low-order Vector Multiply, Mod...

[Amy Kwan via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1dc1a3fb0c51527d46ca47ae794ace16c8ec2fd2
      https://github.com/llvm/llvm-project/commit/1dc1a3fb0c51527d46ca47ae794ace16c8ec2fd2
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2020-07-23 (Thu, 23 Jul 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    A llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
    A llvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
    A llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

  Log Message:
  -----------
  [PowerPC] Implement low-order Vector Multiply, Modulus and Divide Instructions

This patch aims to implement the low order vector multiply, divide and modulo
instructions available on Power10.

The patch involves legalizing the ISD nodes MUL, UDIV, SDIV, UREM and SREM for
v2i64 and v4i32 vector types in order to utilize the following instructions:
- Vector Multiply Low Doubleword: vmulld
- Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud
- Vector Divide Word/Doubleword: vdivsw, vdivsd, vdivuw, vdivud

Differential Revision: https://reviews.llvm.org/D82510